How to get magnitude of signals in Verilog -
i have module magnitude : module magnitude( input [31:0] re, input [31:0] im, output [31:0] out ); assign out = re * re + im * im; endmodule now, 128 signals, need find out magnitude. is, need way count 128. how can that? also, first verilog code wrote. advice on making efficient welcome. according understanding of question, may intend following: module magnitude( input [31:0] re, input clk; input reset; input [31:0] im, output reg [31:0] out ); reg [6:0] counter; @(posedge clk or negedge reset) begin if(!reset) begin counter<=0; end else begin if (counter==7'd128) counter<=0; else counter<=counter+1; end end @(posedge clk or negedge reset) begin if(!reset) out<=0; else begin if (counter==7'd127) out<=0; // counter counts 128, become zero. else out <= out + re * re + im * im; end end endmodule
