vhdl signal assignment in a testbench -

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even after doing extensive research in web, have not come across clean explanation of how signal assignment happens in vhdl testbench wait statements.

could please elaborate how work?

for e.g. within process have this:

wait until spi_sck = '1'; wait until spi_sck = '0'; tb_rx_bytes(7) <= spi_mosi;

how can make sure tb_rx_byte assignment happens?

more specifically, problem last tb_rx_bytes not set spi_mosi assignment.

for j in 31 downto 0 loop   wait until spi_sck = '1';   wait until spi_sck = '0';   tb_rx_bytes(j) <= spi_mosi; end loop;

in order see effect of signal assignment 3 conditions must hold successively:

  1. there event (value change) on spi_sck , new value '1'
  2. there event (value change) on spi_sck , new value '0'
  3. some physical time elapses such assignment has visible effect

i guess last condition fails , prevents last assignment having visible effects. add wait 1 ns; after end loop; statement.


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