How to create a counter within a counter using verilog? -

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for project, need write values address display on screen. means need 2 counters, 1 row value , 1 column value. usually, when work java, use nested loops. in verilog, logic isn't going work well. figure out how put counter inside of counter?

a set of nested counters can implemented instead series of counters. have first counter increment usual. then, value of first counter (perhaps when loops 0), increment second counter.

(i.e. [0,m-1] -> [1,0], first counter ranges {0,m-1})


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