vhdl - ERROR: Signal signal_led cannot be synthesized, bad synchronous description -
i don't understand why error:
warning:xst:819 "c:/users/aa/desktop/tools/mycoursedesign/control.vhd" line 52: 1 or more signals missing in process sensitivity list. enable synthesis of fpga/cpld hardware, xst assume necessary signals present in sensitivity list. please note result of synthesis may differ initial design specification. missing signals are:
<signal_led>, <signal_q0>, <signal_q1>, <signal_q2>, <signal_q3>, <signal_q4>
error:xst:827 - "c:/users/aa/desktop/tools/mycoursedesign/control.vhd" line 52: signal signal_led cannot synthesized, bad synchronous description. description style using describe synchronous element (register, memory, etc.) not supported in current software release.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity control port ( clkadd,clksub: in std_logic;--脉冲 --模式 model : in std_logic; r : in std_logic;--置0端 --led端输出 3位对应 led : out std_logic_vector (2 downto 0); --q0-q4实现5个数码管的bcd码输出 q0 : out std_logic_vector (3 downto 0); q1 : out std_logic_vector (3 downto 0); q2 : out std_logic_vector (3 downto 0); q3 : out std_logic_vector (3 downto 0); q4 : out std_logic_vector (3 downto 0)); end control; architecture behavioral of control --signal 是全局量(只支持逻辑运算) -- variable是局部进程变量 --满位标志 signal isfull:std_logic_vector(4 downto 0); --0位标志 signal iszero:std_logic_vector(4 downto 0); --数码管中继信号 signal signal_q0,signal_q1,signal_q2,signal_q3,signal_q4:std_logic_vector(3 downto 0); --led灯表示选中状态 signal signal_led:std_logic_vector(2 downto 0); begin --规定model为0时为移位操作，为1时为调数操作 --加减数 p_main:process(clkadd,clksub,r) begin --清0 if(r='1')then signal_led<="000"; signal_q0<="0000"; signal_q1<="0000"; signal_q2<="0000"; signal_q3<="0000"; signal_q4<="0000"; --加信号 elsif(clkadd'event , clkadd='1')then --左移模式 if(model='0')then if(signal_led="100")then signal_led<="000"; else signal_led<=signal_led+1; end if; --加数模式 elsif(model='1')then signal_led<=signal_led; if(signal_led="000")then --进位 if(signal_q0="1001")then if(isfull="11111")then signal_q0<=signal_q0; --处理进位 else signal_q0<="0000"; --二次进位 if(signal_q1="1001")then signal_q1<="0000"; --三次进位 if(signal_q2="1001")then signal_q2<="0000"; --四次进位 if(signal_q3="1001")then signal_q3<="0000"; signal_q4<=signal_q4+1; else signal_q3<=signal_q3+1; end if; else signal_q2<=signal_q2+1; end if; else signal_q1<=signal_q1+1; end if; end if; else --加数 signal_q0<=signal_q0+1; end if; elsif(signal_led="001")then --进位 if(signal_q1="1001")then if(isfull(4 downto 1)="1111")then signal_q1<=signal_q1; else signal_q1<="0000"; --处理进位 if(signal_q2="1001")then signal_q2<="0000"; --二次进位 if(signal_q3="1001")then signal_q3<="0000"; signal_q4<=signal_q4+1; else signal_q3<=signal_q3+1; end if; else signal_q2<=signal_q2+1; end if; end if; else --加数 signal_q1<=signal_q1+1; end if; elsif(signal_led="010")then --进位 if(signal_q2="1001")then if(isfull(4 downto 2)="111")then signal_q2<=signal_q2; else signal_q2<="0000"; if(signal_q3="1001")then signal_q3<="0000"; signal_q4<=signal_q4+1; else signal_q3<=signal_q3+1; end if; end if; else --加数 signal_q2<=signal_q2+1; end if; elsif(signal_led="011")then --进位 if(signal_q3="1001")then if(isfull(4 downto 3)="11") signal_q3<=signal_q3; else signal_q3<="0000"; signal_q4<=signal_q4+1; end if; else --加数 signal_q3<=signal_q3+1; end if; elsif(signal_led="100")then --进位 if(signal_q4="0001")then signal_q4<=signal_q4; else --加数 signal_q4<=signal_q4+1; end if; end if; end if; --减信号 elsif(clksub'event , clksub='1')then --右移模式 if(model='0')then if(signal_led="000")then signal_led<="100"; else signal_led<=signal_led-1; end if; --减数模式 elsif(model='1')then signal_led<=signal_led; if(signal_led="000")then if(signal_q0="0000")then if(iszero(4 downto 0)="11111")then signal_q0<=signal_q0; else --借位 if(signal_q1="0000")then signal_q1<="1001"; --二次借位 if(signal_q2="0000")then signal_q2<="1001"; --三次借位 if(signal_q3="0000")then signal_q3<="1001"; signal_q4<=signal_q4-1; else signal_q3<=signal_q3-1; end if; else signal_q2<=signal_q2-1; end if; else signal_q1<=signal_q1-1; end if; end if; else signal_q0<=signal_q0-1; end if; elsif(signal_led="001")then if(signal_q1="0000")then if(iszero(4 downto 1)="1111")then signal_q1<=signal_q1; else --借位 if(signal_q2="0000")then signal_q2<="1001"; --二次借位 if(signal_q3="0000")then signal_q3<="1001"; signal_q4<=signal_q4-1; else signal_q3<=signal_q3-1; end if; else signal_q2<=signal_q2-1; end if; end if; else signal_q1<=signal_q1-1; end if; elsif(signal_led="010")then if(signal_q2="0000")then if(iszero(4 downto 2)="111")then signal_q2<=signal_q2; --借位 else signal_q2<="1001"; if(signal_q3="0000")then signal_q3<="1001"; signal_q4<=signal_q4-1; else signal_q3<=signal_q3-1; end if; end if; else signal_q2<=signal_q2-1; end if; elsif(signal_led="011")then if(signal_q3="0000")then if(iszero(4 downto 3)="11")then signal_q3<=signal_q3; else signal_q3<="1001"; signal_q4<=signal_q4-1; end if; else signal_q3<=signal_q3-1; end if; elsif(signal_led="100")then if(signal_q4="0000")then signal_q4<=signal_q4; else signal_q4<=signal_q4-1; end if; end if; end if; end if; led<=signal_led; q0<=signal_q0; q1<=signal_q1; q2<=signal_q2; q3<=signal_q3; q4<=signal_q4; end process p_main; --数位监控 level0:process(signal_q0) begin if(signal_q0="0000")then iszero(0)<='1'; else iszero(0)<='0'; end if; if(signal_q0="1001")then isfull(0)<='1'; else isfull(0)<='0'; end if; end process level0; level1:process(signal_q1) begin if(signal_q1="0000")then iszero(1)<='1'; else iszero(1)<='0'; end if; if(signal_q1="1001")then isfull(1)<='1'; else isfull(1)<='0'; end if; end process level1; level2:process(signal_q2) begin if(signal_q2="0000")then iszero(2)<='1'; else iszero(2)<='0'; end if; if(signal_q2="1001")then isfull(2)<='1'; else isfull(2)<='0'; end if; end process level2; level3:process(signal_q3) begin if(signal_q3="0000")then iszero(3)<='1'; else iszero(3)<='0'; end if; if(signal_q3="1001")then isfull(3)<='1'; else isfull(3)<='0'; end if; end process level3; level4:process(signal_q4) begin if(signal_q4="0000")then iszero(4)<='1'; else iszero(4)<='0'; end if; if(signal_q4="0001")then isfull(4)<='1'; else isfull(4)<='0'; end if; end process level4; end behavioral;
your problem boils down this:
process (clk_add, clk_sub, r) begin if (r = '1') -- reset elsif (rising_edge(clk_add)) -- assign signal_led elsif (rising_edge(clk_sub)) -- assign signal_led end if; end process; the basic problem here have signal_led being assigned edges of 2 different clocks in 1 process. there isn't in fpga can replicate this; there's no such thing dual-clock register in fpga, hence 'bad synchronous description'. need rewrite code use 1 clock in each process, how depends on timing between clk_add, clk_sub, , other inputs.
one example of might like:
process (clk, r) begin if (r = '1') -- reset some_signal <= 0; elsif (rising_edge(clk)) if (add = '1') some_signal <= some_signal + 1; elsif (sub = '1') some_signal <= some_signal - 1; end if; end if; end process; i haven't included declarations or tried match intended function of code, should give right idea.
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